On February 13, VeriSilicon Co., Ltd. (688521.SH) said in an interview with specific objects that as all walks of life enter a critical period of artificial intelligence upgrading, the market demand for large computing power has increased sharply. Against this backdrop, the IC industry is undergoing a transformation from SoC (System-on-a-Chip) to SiP (System-in-Package), which is driven by the improvement of high-performance single-chip integration and complexity, performance and power optimization, yield and design/manufacturing cost improvements, and other considerations. In order to adapt to this development trend, VeriSilicon is upgrading its semiconductor IP (intellectual property), which plays an important role in SoCs, to Chiplet, the core component of SiP, and building a chip design service platform based on Chiplet architecture.

VeriSilicon has helped customers design high-end application processors based on Chiplet architecture, using MCM advanced packaging technology to package high-performance SoCs and multiple IPM memories. It has helped customers design 2.5DCoWos packages for high-computing AIGC chips, and has designed and developed UCIe/BoW-compatible physical layer interfaces for die-to-die connections. It has cooperated with Lanyang Intelligence, an industry leader in chiplet chip solutions, to provide it with a variety of VeriSilicon's own processor IPs, including GPGPU, NPU and VPU, to help it deploy high-performance AI chips based on Chiplet architecture, which are targeted at data centers, high-performance computing, automotive and other applications.

One of the company's refinancing and investment projects is the "Chiplet Solution Platform R&D Project in the Field of AIGC and Smart Mobility", and forms a software and hardware chip design platform based on Chiplet architecture, which improves the company's existing technology as follows: 1) Combined with the company's IP technology, chip software and hardware design capabilities, etc., new high-computing power GPGPU Chiplet, AI Chiplet and main control Chiplet; 2) Added Die to Die interface IP and related software protocol stack; 3) Strengthen the design and application capabilities of advanced packaging technology; 4) Develop a scalable software and hardware architecture with large computing power based on Chiplet architecture.