(Yicai) July 6 -- The president of Huawei Technologies’ semiconductor business department has released measured data and engineering details of the Tau (τ) Scaling Law, which proposes to replace geometric scaling with time (τ) scaling as a new principle for the evolution of both semiconductors and electronics systems.

He Tingbo updated her paper on the ChinaRxiv platform, adding measured data and engineering details to support the τ Scaling Law and further refining the evolution path of Kirin processors and the Ascend artificial intelligence platform in the coming years. The paper has received over 260,000 clicks and over 50,000 downloads.

The τ Scaling Law advocates for the continuous compression of signal propagation time at multiple levels from devices, circuits, and chips to systems through technologies such as LogicFolding, Unified Bus, and Hi-ONE optical interconnects to achieve continuous improvement in performance, energy efficiency, and system integration, rather than continuing to pursue the extreme reduction of transistor size as in the past few decades.

Huawei’s Kirin 2026 chip has achieved a single-generation leap in the same process node, according to the paper. The transistor density jumped to 238 from 155 MTr/mm², which previously required three years of geometric scaling, the core power efficiency of System-on-a-Chip performance surged 41 percent, and the maximum clock frequency rose nearly 13 percent.

The core frequency of the Kirin central processing unit performance was restored to 3.1 gigahertz this year and is expected to rise to 4 GHz and above by 2029.

In the data center scenario, Huawei’s Unified Bus solution cuts the end-to-end remote access latency by about 500 times from tens of microseconds under the traditional Transmission Control Protocol/Internet Protocol architecture to about 100 nanoseconds. At the rack scale, this brings the system asymptotically close to a single, fabric-coherent machine -- designated internally at Huawei as a System-as-One-Chip.

The single module bandwidth of the near-package optical interconnect solution Hi-ONE reaches 8 terabytes per second, matching the bandwidth of the Unified Bus of AI chips, and expanding the required transmission distance from less than one meter to 100 meters.

“The framework for technological development in the next decade is already clear, but there are still many unresolved issues that cannot be overcome by a single enterprise alone,” He said. “Areas such as toolchain, industry standards, performance benchmarks, device physics, and business models require industry-wide collaboration and co-creation.”

Editor: Futura Costaglione